TRON08008 2013 Programmable Logic Technology

General Details

Full Title
Programmable Logic Technology
Transcript Title
Programmable Logic Technology
Code
TRON08008
Attendance
N/A %
Subject Area
TRON - Electronics
Department
MENG - Mech. and Electronic Eng.
Level
08 - NFQ Level 8
Credit
05 - 05 Credits
Duration
Semester
Fee
Start Term
2013 - Full Academic Year 2013-14
End Term
9999 - The End of Time
Author(s)
Fergal Henry, Ian Craig
Programme Membership
SG_ETRON_K08 201300 Bachelor of Engineering (Honours) in Electronic Engineering SG_EELEC_N08 201300 Level 8 Certificate in Engineering in Electronic Engineering
Description

On completion, the learner will have been exposed to current programmable logic technologies in terms of features, architecture and use of design tools.  Users will implement a set of logic designs from concept/brief through to implementation.

Learning Outcomes

On completion of this module the learner will/should be able to;

1.

Research and evaluate main aspects of programmable logic ICs available on the market

2.

Describe and compare various architectures of modern FPGAs.

3.

Develop an awareness of typical applications of FPGAs

4.

Use a design environment to perform simulation and synthesis of project solutions

5.

Develop, implement and test logic solutions to prescribed logic problems using VHDL

 

Indicative Syllabus

 

Introduction to FPGA's: Fundamental Concepts, The Origin of FPGA's, Alternative Architectures, The Vendors.

Examination of CPLDs and uses in the electronics industry.  How they differ from FPGAs

Programming/Configuring FPGA's.

Design Flows: Schematic, HDL, SVP, C, DSP, Embedded Processor.

FPGA Design Tools: Simulation, Synthesis, Verification.

Introduction to VHDL.

Basic Language Concepts: Simulation and Synthesis.

Modelling Behaviour: Simulation, Synthesis and Structure.

Subprograms, Packages and Libraries.

Identifiers, Data Types and Operators.

Sequential Statements.

Resolved Signals.

Files and Input/Output.

Indicative Practicals/Projects

Various lab exercises using FPGA target board and Xilinx/Altera software to simulate/synthesize Combinational Logic Functions, Sequential Logic Functions, State Machines, etc.

Use of LabVIEW FPGA to carry out various practical tasks.

Use of Altera Quartus II to design FPGA solutions

Coursework & Assessment Breakdown

Coursework & Continuous Assessment
40 %
End of Semester / Year Formal Exam
60 %

Coursework Assessment

Title Type Form Percent Week Learning Outcomes Assessed
1 Practical assessments Continuous Assessment Assessment 20 % OnGoing 4,5
2 Written assignments based on research Continuous Assessment Written Report 20 % OnGoing 1,2,3
             

End of Semester / Year Assessment

Title Type Form Percent Week Learning Outcomes Assessed
1 Final Exam Can include practical exam Final Exam Closed Book Exam 60 % End of Term 1,2,3,4,5
             
             

Full Time Mode Workload


Type Location Description Hours Frequency Avg Workload
Lecture Not Specified Theory 2 Weekly 2.00
Practical Engineering Laboratory Practical 2 Weekly 2.00
Total Full Time Average Weekly Learner Contact Time 4.00 Hours

Part Time Mode Workload


Type Location Description Hours Frequency Avg Workload
Lecture Distance Learning Suite Theory 2 Weekly 2.00
Practical Distance Learning Suite Practical work 2 Weekly 2.00
Total Part Time Average Weekly Learner Contact Time 4.00 Hours

Module Resources

Non ISBN Literary Resources

None

Other Resources

As this is a growth area in electronics, it is proposed that a guest speaker with experience of this area from industry would be invited to speak on their views and experiences

Additional Information

None